The I2C_Devicetree reference design project uses a programmable System-on-Chip (SoC) with a Cortex-M0 CPU, in a small 28 Pin TSSOP package, to emulate an I2C EEPROM using the FLASH memory of the SoC, which creates an "intelligent memory" device. The I2C_Devicetree reference design project is intended to make it easier for people to create their own custom expansion boards for Beaglebone, Raspberry Pi, FMC/IPMI, and other platforms that require the use of a I2C EEPROM for automatic product identification, pin mapping, and configuration.Consider a typical development situation, using something like a Beaglebone Black, where you have a main CPU/SoC board, and several expansion boards (i.e. "Capes") attached. In order to support the Devicetree configuration, each expansion board ("Cape") will contain a small I2C EEPROM that holds the Devicetree data structure (i.e. the overlay). This is a fairly common configuration, and it doesn't really matter what the Cape function is for this discussion, it could be a peripheral like an LCD display, Wi-Fi Radio, Motor Controller, Sensor Hub, etc. We are interested here in describing their interconnections, as shown by the block diagram below :
As you can see in the above block diagram, the "orange" colored blocks represent the connections on the I2C bus that will be used to read the Devicetree data structures (i.e. the Overlays) for each expansion board (i.e. Cape/Shield/Plate), in order to determine their make and model, and how they are interfaced and connected.
The I2C_Devicetree reference design project uses a programmable System-on-Chip (SoC), to replace the I2C EEPROM's in the above diagram, and adds some basic interface capability in the process. The I2C_Devicetree reference design project also includes an I2C I/O Expander to provide extra GPIO pins that are I2C controlled, and dual UARTS for host and peripheral serial bridge operations.
- Programmable System-on-Chip
- 28 Pin TSSOP Package
- I2C EEPROM Emulation (32kb - 512kb)
- Programmable I2C Address
- I2C I/O Expander Function
- Dual (2) UARTS (Host & Slave devices at different baud rates)
- Support for LED status indictors
The I2C_Devicetree reference design project creates an "intelligent memory" device by using a microprocessor to emulate a "dumb" I2C EEPROM memory chip. New peripherals for small computers based on the Linux Operating System, such as Beagebone Black "Capes", Raspberry Pi "Hats", and others require a small I2C memory device to be included that holds configuration data about that peripheral. This configuration "meta-data" includes things such as the product make, model, and serial number, and more. The I2C_Devicetree reference design project gives a template design for an "intelligent memory" device, which also includes a GPIO expander and bridge communications functions, including UART(s) and other interfaces for a high level of integration.
I2C_Devicetree Application Examples:
- Beaglebone Black "Cape"
- Raspberry Pi "Hat"
- FPGA Mezzanine Bus Connector "FMC"
- Intelligent Peripheral Manangment Interface "IPMI"
- ThingSoC "Socket"
- I2C_Devicetree is an open source hardware (OSHW) project.
- The User simply changes a project define to select the output EEPROM format.
- Beaglebone, RaspPi, IPMI/FMC, and Custom EEPROM formats supported.
- 6/2015 Early Access - Version 0.1
Version 0.1 only supports IPMI FRU EEPROM format (FMC/IPMI)
Version 0.2 adds support for Beaglebone Black Cape EEPROM format
Version 0.3 adds support for Raspberry Pi HAT EEPROM format
Version 0.4 adds support for Flattened Devicetree (FDT) format
- 7/2015 Beta Schedule depends directly on User/Vendor Interest and Support.
User/Vendor Interest and Feedback on this project will directly determine it's support level and priority. If you are interested in using it, please leave comments or email us.
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